AK8130 Datasheet, PDF (4/8 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with VCXO

AK8130
The brand name
of AKEMD’s IC’s
DC Characteristics
All specifications at VDD: over 3.0 to 3.6V, Ta: -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Current 1
Input Current 2
High Level Output
Voltage
Low level Output
Voltage
Current Consumption
Symbol
VIH
VIL
IL1
IL2
VOH
VOL
IDD
Conditions
MIN
Pin: S0,S1,S2
0.7VDD
Pin: S0,S1,S2
Pin: S0,S1,S2
-20
PIN: VIN
-3
Pin: CLK1-4, REFOUT
IOH=-4mA
0.8VDD
Pin: CLK1-4, REFOUT
IOL=+4mA
Clock out selection by note ⁽¹⁾
No load,Ta=25℃
TYP
16.5
MAX Unit
V
0.3VDD V
+10 μA
+3
μA
V
0.2VDD V
mA
(1) Pin setting for output clock selection: [S2:S0] = HLH
AC Characteristics
All specifications at VDD: over 3.0 to 3.6V, Ta: over -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP MAX Unit
Crystal Clock Frequency
VCXO Pullable Range ⁽³⁾
VIN at over 0 to VDD V
±110
27.0000
MHz
ppm
VCXO Gain
Period Jitter ⁽⁴⁾
GVCXO
VIN range at 1.5V±1.0V
CLK1-4
150
ppm/
V
150
ps
Long Term Jitter ⁽⁵⁾
Output Clock Duty
Cycle
CLK1 at 54.000MHz
1000 cycle delay
CLK1 at 74.250MHz
1000 cycle delay
REFOUT at 27.000MHz
1000 cycle delay
Pin: CLK1-4 ⁽¹⁾
Pin: REFOUT ⁽²⁾
0.5
ns
0.85
ns
160
ps
45
50
55
%
40
50
60
%
Output Clock Rise Time
Output Clock Fall Time
Power-up Time
Pin: CLK1-4 ⁽¹⁾
trise
Pin: REFOUT ^{(2 )}
Pin: CLK1-4 ⁽¹⁾
tfall
Pin: REFOUT ^{(2 )}
Pin: CLK1-4 ⁽¹⁾
1.5
ns
2.5
ns
1.5
ns
2.5
ns
5
ms
Output Transition Time ⁽⁶⁾
Pin: CLK1 at
74.25 or 74.175MHz
200
µs
(1) Measured with load capacitance of 15pF
(2) Measured with load capacitance of 25pF
(3) Pullable range depends on crystal characteristics, on-chip load capacitance, and stray capacity of PCB.
Min. ±110ppm is applied to AKEMD’s authorized test condition.
(4) ±3σ in 1000 sampling or more
(5) ±3σ in 5000 sampling or more
(6) Time to settle output into ±20ppm of specified frequency
Feb-08
MS0598-E-03
-4-