AK6510C Datasheet, PDF (4/17 Pages) Asahi Kasei Microsystems – SPI bus 32K/64Kbit Serial CMOS EEPROM

ASAHI KASEI
[AK6510C/12C]
Pin Description
CS (Chip Select Input)
When CS changes high level to low level, the AK6510C/12C can receive the instructions.
CS should be kept low level while receiving op-code, address and data, and while outputting
data.
When CS is high level, SO indicate Hi-Z.
SCK (Serial Clock Input)
The SCK clock pin is the synchronous clock input for input/output data.
SI (Serial Data Input)
The op-code, address, and data are written to the SI pin.
SO (Serial Data Output)
The SO pin outputs the data from memory array and status register.
WP (Write Protect Input)
The WP pin controls the write function to the status register.
When the WPEN bit in the status register is "0", the function of WP pin becomes disable.
Then the status register can be programmable when the WEN bit in the status register is "1".
And it does not depend on the status of WP pin.
When the WPEN bit is "1", the function of WP is enabled. Then the status register can not
be programmable when the WEN bit is "1" and the status of WP pin is low.
When the WPEN bit is "1", WP pin is high and WEN bit is "1", AK6510C/12C can accept the
WRITE instruction to the status registers.
During the instruction input, WP pin should keep high or low level.
HOLD (Hold Input)
The HOLD pin can hold the data transfer. When the HOLD pin changes hi to low while the
SCK is low, the data transfer is held. And the transfer starts when the HOLD pin changes
low to high while the SCK is low. While the holding the data transfer, AK6510C/12C ignores
the clock signal on SCK pin.
DAP02E-04
-4-
2005/03