AK2048D Datasheet, PDF (4/16 Pages) Asahi Kasei Microsystems – 2M CMI Transceiver

ASAHI KASEI
[AK2048]
PIN DESCRIPTIONS
Pin Name
RDATA
RCLK
RCRV
TDATA
TCLK
TCRV
TEST1
TEST2
LOCK
I/O
Function
O ^{Receive Data output recovered from the incoming data. Delay time from the incoming}
data to the RDATA is about 1.25bit. Output on the rising edge of RCLK.
O ^{Receive Clock Output recovered from the incoming data.}
O ^{CRV (Code Rule Violation) output pin.}
When AK2048D detects the CRV of CMI codes from in the coming data, RCRV goes
to “high” synchronized with the violation data. CRV is detected for both “0” data and
“1” data. Refer to Fig.6, 11
I ^{Transmit Data Input pin.}
Input on the falling edge of TCLK.
I ^{Transmit Clock Input pin.}
I ^{If this input is “high”, AK2048D generates CRV in the transmit data.}
CRV is generated for both “0”data and “1”data. “High” input TCRV is accepted until 5
clocks duration. If the duration of “High” input is longer than 6 clocks, TCRV input
after 6th clock is ignored. Refer to Fig.4, 11
NC ^{Test pin. Should be floated.}
NC ^{Test pin. Should be floated.}
O ^{LOCK indicates the PLL status whether PLL is in the LOCK status or PLL is in the}
UNLOCK status.
LOCK status
LOCK becomes “Low” when the sampled RCLK are all “Low” during the consecutive
32 RXA-RXB sample clock duration.
UN LOCK status
LOCK becomes “High” when the following both conditions are satisfied.
- The sampled RCLK are “High” more than 5 clocks in the frame of the consecutive
256 RXA-RXB clock duration.
- And the above happens in the 5 consecutive frames.
In another condition, LOCK keeps the current output status without change.
The output timing of this signal is asynchronous with RCLK.
When RST is “Low”, LOCK is fixed to “High”.
MS0073-E-00
4
2001/01