AKD5355 Datasheet, PDF (3/19 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK5355

ASAHI KASEI
[AKD5355]
(3) Evaluation of A/D using DIT at MCLK=384fs.
PORT1 (DIT) is used. On board DIT (AK4103) is set to the master mode. The AK4103 provides BICK and
LRCK to the AK5355 from an external master clock (MCLK). When using an external clock through a BNC
connector (J3), select “EXT” on JP4 (CLK) and short JP3 (XTE). (Refer to a Table 1 ∼ 3 for the set up of the DIP
switch. The master mode should be selected in Table 2.)
JP4
JP6
CLK
BICK
256-64fs
XTL
EXT
256-32fs
512-64fs
512-32fs
JP7
JP3
LRCK
XTE
256fs 512fs
„ Jumpers Set up
1. JP1 (VD) : VD pin of the AK5355
VA : Supplied from “VA” connector via 10Ω.
VD : Supplied from “VD” connector.
2. JP2 (GND) : Connection between AGND and DGND.
OPEN : Both grounds are separated on board.
SHORT : Both grounds are connected on board.
„ DIP switch set up
[SW2]: Set up of AK5355 and AK4103 (Refer to the datasheet)
No.
Pin
default
Mode
1
SEL
L
H: Input Gain +15dB
L: Input Gain +0dB
2 5355_DIF
L
H:I2S
L:16bit Left justified
3 4103_DIF1
L
4 4103_DIF0
L
See Table 2
5
CKS1
L
6
CKS0
H
See Table 3
Table 1. Set up for AK5355 and AK4103
4103_DIF1
OFF
OFF
ON
ON
4103_DIF0
Mode
OFF
24bit, Left justified
ON
24bit, I²S
OFF
24bit, Left justified
ON
24bit, I²S
Table 2. Set up of Interface Format
Clock mode
Slave mode
Master mode
<KM066402>
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