AKD4394 Datasheet, PDF (3/21 Pages) Asahi Kasei Microsystems – EVALUATION BOARD REV.C FOR AK4394

ASAHI KASEI
<The evaluation modes and corresponding jumper pins setting
1. Evaluation Modes
•Applicable Evaluation Mode
(1) DIR(Optical Link)
(2) Ideal sine wave generated by ROM data
(3) Using AD converted data
(4)All interface signals including master clock are fed externally.
[AKD4394]
(1) DIR(Optical Link) (default)
PORT2 is used for the evaluation using such as CD test disk. The DIR generates MCLK, BICK and LRCK SDATAfrom
the received data through optical connector(PORT2: TORX176).
JP4
JP1 JP2
VDD
INV
XTL
GND
CS8414
THR
BCP
(MSB
justified)
INV
THR
BCP
(others)
JP5
JP6
JP7 ^JP8
JP14
XTL/EXT
DIR
2X
1/2X
DIR
XTL/EXT
1X
1X
SD
BI
LR
CKDIV1 CKDIV2
Fig.3 Jumper set-up (DIR)
JP9
DIR
XTL
EXT
CLK
(2) Ideal sine wave generated by ROM data
Digital signal generated by AKD43XX are used. PORT1 is used for the interface with AKD43XX. Master clock is sent
from AKD4394 to AKD43XX then LRCK, BICK and SDATA are sent from AKD43XX to AKD4394.
JP1
JP2
JP4
JP5
VDD
GND
XTL
C S 8414
INV
THR
BCP
X T L /E X T
D IR
BI
JP6
JP7
D IR
X T L /E X T
SD
LR
JP8
J P 14
JP9
D IR
2X
1/2X
1X
1X
XTL
C K D IV 1 C K D IV 2
EXT
CLK
Fig.4 Jumper set-up (ROM data)
<KM063001>
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