AKD4117 Datasheet, PDF (3/20 Pages) Asahi Kasei Microsystems – AK4117 Evaluation Board Rev.0

ASAHI KASEI
a-3. Set-up of AK4117 input path
IPS bit
Input data
0
RX0
1
RX1
Table 3. Recovery Data Select
Default
[AKD4117-B]
b. Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
PORT2
DIR
1
5
10
6
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The AK4117 has a master clock output pin, MCKO. In PLL mode, PCKS1-0 bits select the MCKO frequency as
shown in Table 4. When MCKO=512fs, MCKO goes to “L” when fs=96kHz and 192kHz. When MCKO=256fs,
MCKO goes to “L” when fs=192kHz. When LP bit is set to “1”, the AK4117 is in low power mode (default). In
low power mode, PLL lock range is up to 48kHz and the MCKO frequency is fixed to 256fs.
In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit
selects the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 5).
LP
PCKS1
PCKS0
MCKO
fs [kHz]
0
0
512fs
32 ∼ 48
0
0
1
256fs
32 ∼ 96
1
0
128fs
32 ∼ 192
1
1
N/A
N/A
1
x
x
256fs
32 ∼ 48
Default
Table 4. Master Clock Frequency Select
(PLL mode: Clock operation mode 0, 2(UNLCK=0))
XCKS1 XCKS0
0
0
0
1
1
0
1
1
X’tal
or
EXT
128fs
256fs
512fs
1024fs
MCKO
DIV=0
128fs
256fs
512fs
1024fs
DIV=1
64fs
128fs
256fs
512fs
fs [kHz]
EXTCLK [MHz]
X’tal [MHz]
2.048 4.096 8.192 11.2896 12.288 24.576
16
32
64
88.2
96
192
8
16
32
44.1
48
96
N/A
8
16
N/A
N/A
48
N/A
N/A
8
N/A
N/A
N/A
Default
Table 5. Master Clock Frequency Select
(X’tal mode: Clock operation mode 1, 2(UNLCK=1), 3)
<KM077200>
-3-
2004/12