AKD4103A Datasheet, PDF (3/19 Pages) Asahi Kasei Microsystems – AK4103A Evaluation Board Rev.0

ASAHI KASEI
[AKD4103A-B]
CKS1 pin
(SW3_5)
CKS1 bit
CKS0 pin
(Sub_JP19)
CKS0 bit
MCLK
fs (max)
0
0
128fs
28k-192 kHz
0
1
256fs
28k-108 kHz
1
0
384fs
28k-54 kHz
1
1
512fs
28k-54 kHz
Table 3. Master Clock Frequency Select
Default
b-1. Set-up of input/output of BICK and LRCK
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4103A (Refer to Table 5).
Audio format
SW3_8 (DIT_I/O)
Slave mode
0
Master mode
1
Table 4. Set-up of DIT_I/O
Default
c. Set-up of audio data format
It sets up by SW 1_2, SW 1_3 and SW1_4 in synchronous mode. Please set up DIF2-0 bit in asynchronous
mode.
Mode
0
1
2
3
4
5
6
7
DIF2 pin
(SW1_4)
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 pin
(SW1_3)
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 pin
(SW1_2)
SDTI
DIF0 bit
0
24bit, Left justified
1
24bit, Left justified
0
24bit, Left justified
1
24bit, Left justified
0
24bit, Left justified
1
24bit, I²S
0
24bit, Left justified
1
24bit, I²S
Table 5. Audio format
LRCK
I/O
H/L O
H/L O
H/L O
H/L O
H/L O
L/H O
H/L I
L/H I
BICK
I/O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64fs
O
64-128fs I
64-128fs I
Default
<KM076800>
-3-
2004/11