AKD4101A Datasheet, PDF (3/24 Pages) Asahi Kasei Microsystems – AK4101A Evaluation Board Rev.0

ASAHI KASEI
[AKD4101A-B]
b. Set-up of clock input and output
The used signals are MCLK, LRCK, BICK and SDTI (DAUX).
The signal level outputted and inputted from PORT5 is 5V.
Clock
PORT
MCLK
PORT5
BICK
PORT5
LRCK
PORT5
SDTI
(DAUX)
PORT5
Table 3. Clock input/output
CKS1 pin
(SW3_5)
CKS1 bit
CKS0 pin
(Sub_JP20)
CKS0 bit
MCLK
fs (max)
0
0
128fs
28k-192 kHz
0
1
256fs
28k-108 kHz
1
0
384fs
28k-54 kHz
1
1
512fs
28k-54 kHz
Table 4. Master Clock Frequency Select
Default
b-1. Set-up of input/output of BICK and LRCK
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4101A (Refer to Table 6).
Audio format
SW3_8 (DIT_I/O)
Slave mode
0
Master mode
1
Table 5. Set-up of DIT_I/O
Default
c. Set-up of audio data format
It sets up by SW 1_2, SW 1_3 and SW1_4 in synchronous mode. Please set up DIF2-0 bit in asynchronous
mode.
Mode
0
1
2
3
4
5
6
7
DIF2 pin
(SW1_4)
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 pin
(SW1_3)
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 pin
(SW1_2)
SDTI
DIF0 bit
0
16bit, Right justified
1
18bit, Right justified
0
20bit, Right justified
1
24bit, Right justified
0
24bit, Left justified
1
24bit, I²S
0
24bit, Left justified
1
24bit, I²S
Table 6. Audio format
LRCK
I/O
H/L I
H/L I
H/L I
H/L I
H/L I
L/H I
H/L O
L/H O
BICK
I/O
64fs
I
64fs
I
64fs
I
64fs
I
64fs
I
64fs
I
64-128fs O
64-128fs O
Default
<KM080100>
-3-
2005/10