AK6512CA Datasheet, PDF (3/17 Pages) Asahi Kasei Microsystems – SPI bus 64Kbit Serial CMOS EEPROM

ASAHI KASEI
[AK6512CA]
„ Data Transfer
An IC that outputs the clock is called "MASTER", an IC that receives the clock is called "SLAVE".
The AK6512CA operates as a SLAVE. Data is written to the SI pin and read from SO pin. The
MSB is transmitted first.
After CS pin changes high level to low level, AK6512CA receives the first data bit on the SI pin
synchronously with the rising edge of the input pulse of serial clock. While CS pin is high level, the
data input to the SI pin is don’t care and SO pin indicates Hi-Z.
All the functions are organized 8 bits of op-code, address, and data. If there is an invalid op-code,
the AK6512CA ignores the address and data information and SO pin indicates Hi-Z. In order to
input new op-code, CS pin should be toggled.
„ Hold
AK6512CA has a HOLD pin that can hold the data transfer. When HOLD changes high to low
while SCK is low, the data transfer stops. After the HOLD pin changes low to high while SCK is low,
the data transfer starts again. While the data transfer is paused, AK6512CA ignores the clock on
the SCK line.
„ Write Protect
AK6512CA has status registers. When the WPEN bit in the status registers is "1", Write Protect
function is enabled. When WPEN bit is "1" and WP pin is low level, the status register is protected
from write function. When WP pin becomes low level while the WRITE to the status register
instruction is written, the AK6512CA doesn’t accept the instruction. When the WP pin changes low
level while the internal programming, the programming function continues.
When the WPEN bit is "0", WP pin function is disabled. Even if WP pin is fixed to low level, the
WRITE function to the status register can be done. When the WP pin is high level, AK6512CA can
accept all of READ and WRITE functions.
DAP03E-00
-3-
2005/03