AK4101A Datasheet, PDF (22/29 Pages) Asahi Kasei Microsystems – QUAD OUTPUTS 192KHZ 24 BIT DIT

ASAHI KASEI
[AK4101A]
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H-
09H
Register Name
Clock/Format Control
Validity/fs Control
Ch 1 A-channel C-bit
buffer for Byte 0
Ch 1 A-channel C-bit
buffer for Byte 1
Ch 1 A-channel C-bit
buffer for Byte 2
Ch 1 A-channel C-bit
buffer for Byte 3
Ch 1 B-channel C-bit
buffer for Byte 0-3
0AH- Ch 1 A-channel U-bit
0DH buffer for Byte 0-3
0EH-
11H
12H-
15H
16H-
19H
1AH-
1DH
1EH-
21H
22H-
25H
26H-
29H
2AH-
2DH
2EH-
31H
32H-
35H
36H-
39H
3AH-
3DH
3EH-
41H
Ch 1 B-channel U-bit
buffer for Byte 0-3
Ch 2 A-channel C-bit
buffer for Byte 0-3
Ch 2 B-channel C-bit
buffer for Byte 0-3
Ch 2 A-channel U-bit
buffer for Byte 0-3
Ch 2 B-channel U-bit
buffer for Byte 0-3
Ch 3 A-channel C-bit
buffer for Byte 0-3
Ch 3 B-channel C-bit
buffer for Byte 0-3
Ch 3 A-channel U-bit
buffer for Byte 0-3
Ch 3 B-channel U-bit
buffer for Byte 0-3
Ch 4 A-channel C-bit
buffer for Byte 0-3
Ch 4 B-channel C-bit
buffer for Byte 0-3
Ch 4 A-channel U-bit
buffer for Byte 0-3
Ch 4 B-channel U-bit
buffer for Byte 0-3
D7
CRCE
V4
CA7
D6
DIF2
V3
CA6
D5
DIF1
V2
CA5
D4
DIF0
V1
CA4
D3
CKS1
FS3
CA3
D2
CKS0
FS2
CA2
D1
MUTEN
FS1
CA1
D0
RSTN
FS0
CA0
CA15 CA14 CA13 CA12 CA11 CA10 CA9
CA8
CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16
CA31
CB7
…
CB31
UA7
…
UA31
UB7
…
UB31
CA30
…
…
…
…
…
…
CA29
…
…
…
…
…
…
CA28
…
CA27
…
CA26
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
CA25
…
…
…
…
…
…
CA24
CB0
…
CB24
UA0
…
UA24
UB0
…
UB24
…
…
…
…
…
…
…
…
…
…
…
Table 7. Register Map
Notes:
(1) In stereo mode, A indicates Left Channel and B indicates Right Channel.
(2) In asynchronous mode, the DIF2-0 and CKS1-0 bits are logically “ORed” with the DIF2-0 and CKS1-0 pins.
(3) For addresses from 42H to FFH, data is not written.
(4) The PDN pin = “L” resets the registers to their default values.
MS0250-E-00
- 22 -
2003/07