|
AK1572 Datasheet, PDF (22/35 Pages) Asahi Kasei Microsystems – Down Converter Mixer with Fractional-N Frequency Synthesizer and VCO | |||
|
◁ |
[AK1572]
12. Lock Detect
Lock detect output can be selected by {LD} in D [13] of <Address0x04>. When {LD} is set to â1â,
the [LD] pin outputs a phase comparison result which is from phase detector directly. (This is called
âanalog lock detectâ.) When {LD} is set to â0â, the output is the lock detect signal according to the
on-chip logic. (This is called âdigital lock detectâ.)
The digital lock detect can be done as following:
The [LD] pin is in unlocked state (which outputs âLâ) when a frequency setup is made.
In the digital lock detect, the [LD] pin outputs âHâ (which means the locked state) when a phase error
smaller than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error
larger than T is detected for N times consecutively while the [LD] pin outputs âHâ, then the [LD] pin
outputs âLâ (which means the unlocked state). The counter value N can be set by {LDCNTSEL} in D
[14] of <Address0x04>. The N is different between âunlocked to lockedâ and âlocked to unlockedâ.
{LDCNTSEL}
0
1
unlocked to locked
N=15
N=31
locked to unlocked
N=3
N=7
The lock detect signal is shown below
Reference clock
Phase Comparison signal
T/2
Divided VCO signal
Phase detector output signal
This is ignored because it
cannot be sampled.
Valid
ignore
LD output
ignore
d
Valid
ignore
The [LD] pin outputs HIGH when a
phase error which is smaller than T/2
is detected for N times consecutively.
Case of âR = 1â
MS1551-E-00
22
2013/8
|
▷ |