AK5576EN Datasheet, PDF (21/69 Pages) Asahi Kasei Microsystems – 6-Channel Differential 32-bit  ADC

[AK5576]
(Ta= 40 - +105 C; AVDD= 4.75-5.25 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”),
VDD18= 1.7-1.98 V (LDOE pin=“L”), C_L= 10 pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Audio Interface Timing (Slave mode) (Figure 21)
TDM128 mode (TDM1-0 bits = “01”)
BICK Period
Normal Speed mode
tBCK 1/128fsn
-
Double Speed mode
tBCK 1/128fsd
-
Quad Speed mode
tBCK 1/128fsq
-
BICK Pulse Width Low
tBCKL
14
-
BICK Pulse Width High
tBCKH
14
-
LRCK Edge to BICK “↑”
(Note 19) tLRB
14
-
BICK “↑” to LRCK Edge
(Note 19) tBLR
14
-
BICK “↑” to SDTO1/2
tBSDD
5
-
TDMIN Hold Time
tSDH
5
-
TDMIN Setup Time
tSDS
5
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
30
ns
-
ns
-
ns
TDM256 mode (TDM1-0 bits = “10”)
BICK Period
Normal Speed mode
tBCK 1/256fsn
-
Double Speed mode
tBCK 1/256fsd
-
BICK Pulse Width Low
tBCKL
14
-
BICK Pulse Width High
tBCKH
14
-
LRCK Edge to BICK “↑”
(Note 19) tLRB
14
-
BICK “↑” to LRCK Edge
(Note 19) tBLR
14
-
BICK “↑” to SDTO1
tBSDD
5
-
TDMIN Hold Time
tSDH
5
-
TDMIN Setup Time
tSDS
5
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
30
ns
-
ns
-
ns
TDM512 mode (TDM1-0 bits = “11”)
BICK Period
Normal Speed mode
tBCK 1/512fsn
-
BICK Pulse Width Low
tBCKL
14
-
BICK Pulse Width High
tBCKH
14
-
LRCK Edge to BICK “↑”
(Note 19) tLRB
14
-
BICK “↑” to LRCK Edge
(Note 19) tBLR
14
-
BICK “↑” to SDTO1
tBSDD
5
-
TDMIN Hold Time
tSDH
5
-
TDMIN Setup Time
tSDS
5
-
-
ns
-
ns
-
ns
-
ns
-
ns
30
ns
-
ns
-
ns
Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5576
should be reset by the PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
015016912-E-01
- 21 -
2016/01