AK4958ECB Datasheet, PDF (21/35 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/VIDEO-AMP & LDO

[AK4958]
スイッチング特性
(Ta =25C; fs=48kHz; C_L=20pF; AK4958ECB: AVDD=2.8  3.6V, DVDD = 1.6 ~ 2.0V, TVDD = 1.6 or (DVDD-0.2)
3.6V, AK4958ECB: AVDD=2.8  3.6V, DTVDD = 1.6 ~ 2.0V)
Parameter
Symbol
min
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency PLL3-0 bits = “0100”
fCLK
-
PLL3-0 bits = “0110”
fCLK
-
PLL3-0 bits = “0111”
fCLK
-
PLL3-0 bits = “1100”
fCLK
-
PLL3-0 bits = “1101”
fCLK
-
Pulse Width Low
Pulse Width High
tCLKL
tCLKH
0.4/fCLK
0.4/fCLK
MCKO Output Timing
Frequency PS1-0 bits = “00”
fMCK
-
PS1-0 bits = “01”
fMCK
-
PS1-0 bits = “10”
fMCK
-
PS1-0 bits = “11” (Note 33) fMCK
-
Duty Cycle
dMCK
40
LRCK Output Timing
Frequency
Duty Cycle
fs
-
Duty
-
BICK Output Timing
Frequency BCKO bit = “0”
BCKO bit = “1”
fBCK
-
fBCK
-
Duty Cycle
dBCK
-
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
MCKO Output Timing
Frequency PS1-0 bits = “00”
fMCK
-
PS1-0 bits = “01”
fMCK
-
PS1-0 bits = “10”
fMCK
-
PS1-0 bits = “11” (Note 33) fMCK
-
Duty Cycle
dMCK
40
LRCK Input Timing
Frequency
Duty
fs
-
Duty
45
BICK Input Timing
Frequency
Pulse Width Low
Pulse Width High
fBCK
tBCKL
tBCKH
32fs
0.4 x tBCK
0.4 x tBCK
Note 33. MCKO=512fs時はfs=8, 11.025, 12, 16, 32kHzは使用できません。
typ
11.2896
12
24
13.5
27
-
-
256fs
128fs
64fs
512fs
50
Table 6
50
32fs
64fs
50
-
-
-
256fs
128fs
64fs
512fs
50
Table 6
-
-
-
-
max
Unit
-
MHz
-
MHz
-
MHz
-
MHz
-
MHz
-
s
-
s
-
Hz
-
Hz
-
Hz
-
Hz
60
%
-
Hz
-
%
-
Hz
-
Hz
-
%
27
MHz
-
s
-
s
-
Hz
-
Hz
-
Hz
-
Hz
60
%
-
Hz
55
%
64fs
Hz
-
s
-
s
MS1558-J-01-PB
- 21 -
2013/10