AK4103A Datasheet, PDF (21/26 Pages) Asahi Kasei Microsystems – 192 KHZ 24 BIT DIT

ASAHI KASEI
[AK4103A]
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H-
09H
Register Name
Clock/Format Control
Validity/fs Control
A-channel C-bit buffer
for Byte 0
A-channel C-bit buffer
for Byte 1
A-channel C-bit buffer
for Byte 2
A-channel C-bit buffer
for Byte 3
B-channel C-bit buffer
for Byte 0-3
0AH- A-channel U-bit buffer
0DH
for Byte 0-3
0EH- B-channel U-bit buffer
11H
for Byte 0-3
D7
CRCE
0
CA7
CA15
CA23
CA31
CB7
…
CB31
UA7
…
UA31
UB7
…
UB31
D6
DIF2
0
CA6
D5
DIF1
0
CA5
D4
DIF0
V1
CA4
CA14 CA13 CA12
CA22 CA21 CA20
CA30
…
CA29
…
CA28
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
Table 7. Register Map
D3
CKS1
FS3
CA3
CA11
CA19
CA27
…
…
…
…
…
…
D2
CKS0
FS2
CA2
CA10
CA18
CA26
…
…
…
…
…
…
D1
MUTEN
FS1
CA1
CA9
CA17
CA25
…
…
…
…
…
…
D0
RSTN
FS0
CA0
CA8
CA16
CA24
CB0
…
CB24
UA0
…
UA24
UB0
…
UB24
Notes:
(1) In stereo mode, A indicates Left Channel and B indicates Right Channel.
(2) In asynchronous mode, the DIF2-0 and CKS1-0 bits are logically “ORed” with the DIF2-0 and CKS1-0 pins.
(3) For addresses from 12H to FFH, data is not written.
(4) The PDN pin = “L” resets the registers to their default values.
MS0251-E-00
- 21 -
2003/07