AK5538VN Datasheet, PDF (20/70 Pages) Asahi Kasei Microsystems – 8-Channel Differential 32-bit ADC

[AK5538]
(Ta= 40 - +105 C; AVDD= 3.0-3.6 V, TVDD= 1.7-1.98 V (LDOE pin=“L”) or 3.0-3.6 V (LDOE pin=“H”),
VDD18= 1.7-1.98 V (LDOE pin=“L”), C_L= 10 pF)
Parameter
Symbol Min.
Typ.
Max.
Unit
Audio Interface Timing (Slave mode)
Normal mode (TDM1-0 bits = “00”)
(8 kHz  fs  216 kHz) (Figure 19)
(LDOE pin = “H”)
BICK Period
Normal Speed mode
tBCK 1/128fsn
-
Double Speed mode
tBCK 1/128fsd
-
Quad Speed mode
tBCK 1/64fsq
-
BICK Pulse Width Low
tBCKL
32
-
BICK Pulse Width High
tBCKH
32
-
LRCK Edge to BICK “↑”
(Note 19)
tLRB
25
-
BICK “↑” to LRCK Edge
(Note 19)
tBLR
25
-
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
-
-
BICK “↓”to SDTO1/2/3/4
tBSD
-
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
25
ns
25
ns
Normal mode (TDM1-0 bits = “00”)
(8 kHz ≤ fs ≤ 216 kHz) (Figure 19)
(LDOE pin = “L”)
BICK Period
Normal Speed mode (8 kHz ≤ fs ≤ 48 kHz) tBCK 1/128fsn
-
Double Speed mode (48 kHz ≤ fs ≤ 96 kHz) tBCK 1/128fsd
-
Quad Speed mode (96 kHz ≤ fs ≤ 192 kHz) tBCK 1/64fsq
-
BICK Pulse Width Low
tBCKL
36
-
BICK Pulse Width High
tBCKH
36
-
LRCK Edge to BICK “↑”
(Note 19)
tLRB
30
-
BICK “↑” to LRCK Edge
(Note 19)
tBLR
30
-
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
-
-
BICK “↓” to SDTO1/2/3/4
tBSD
-
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
30
ns
30
ns
Normal mode (TDM1-0 bits = “00”)
(fs = 384 kHz, 768 kHz) (Figure 20)
BICK Period
Oct Speed mode
Hex Speed mode
BICK Pulse Width Low
BICK Pulse Width High
LRCK Edge to BICK “↑”
(Note 19)
BICK “↑” to LRCK Edge
(Note 19)
BICK “↑” to SDTO1/2/3/4
tBCK 1/64fso
-
tBCK 1/48fsh
-
tBCKL
12
-
tBCKH
12
-
tLRB
12
-
tBLR
12
-
tBSDD
5
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
22
ns
Note 18. When the 1024fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK5538
should be reset by the PDN pin or RSTN bit.
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
015099878-E-00
- 20 -
2016/03