AKD5383VF Datasheet, PDF (2/22 Pages) Asahi Kasei Microsystems – Evaluation board Rev.B for AK5383VF

ASAHI KASEI
[AKD5383 Rev.B]
n Input buffer circuit
The AKD5383 includes full-differential input buffer circuit with an inverted-amp(gain:-10dB). The capacitor of 10nF
between AIN+ /- decreases the clock feed through noise of modulator, and composes a 1st order LPF(fc=360kHz) with
22ohm resistor before the capacitor. This circuit also has a 1st order LPF(fc=370kHz) composed of op-amp. External
analog signal can be fed through the BNC connector or the Cannon connector.
Analog In
8.1Vpp
4.7k
4.7k ^VP+
47µ
-
+
VP-
NJM5532
VA+
10k
+
10k
10µ
47µ
VA=±5V
VP=±15V
Bias
0.1µ
3k
Bias
3k
910
470p
-
+
910
470p
-
+
Bias
AK5393
22 _2.45Vpp
AIN+
10n
22
AIN-
2.45Vpp
CAL
"L" at self calibration
ZCAL
Figure 1. Full-differential input buffer circuit example
1: In case of using the BNC connector
[JP2,JP3,JP4,JP5]: Short
[R11,R18]:
Open
The resistor value of R10 and R19 should be properly selected in order to much the output
impedance of the signal source.
2: In case of using the Cannon connector
[JP2,JP3,JP4,JP5]: Open
The resistor value of R10, R11, R18 and R19 should be properly selected in order to much the
output impedance of the signal source.
* AKM assumes no responsibility for the trouble when using the above circuit examples.
n Power supply and Decoupling
VA and VD supplies to the AK5383 are decoupled separately in order to minimize the effect of the digital noise. A system
analog supply is fed to VA. VA and VD lines should be distributed separately from the power unit.
Decoupling capacitors are connected to AK5383 as near as possible, particularly the ceramic capacitor to the VREFL/R
pin.
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