AKD4380_04 Datasheet, PDF (2/21 Pages) Asahi Kasei Microsystems – 96kHz sampling 24BitΔΣDAC

ASAHI KASEI
[AKD4380]
„ Analog output
Analog signal is output through BNC connectors on the board. And the output level of AK4380 is 3.45Vpp.
„ Operation sequence
1) Set up the power supply lines.
[VA] (red)
= 4.5 ∼ 5.5V
[VD] (red)
= 4.5 ∼ 5.5V
[AGND] (black) = 0V
[DGND] (black) = 0V
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4380 should be reset once bringing upon power-up
„ Evaluation mode
Applicable evaluation modes
1) DIR (Optical Link and RCA) (default)
2) Using ROM data (AK43XX)
3) Using AKM’s evaluation board for ADC
4) Feeding all signals from external
1) DIR(Optical Link)
PORT3(TORX176) or J3(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,
BICK, LRCK and SDATA from the received data through optical connector (TORX176) or RCA connector.
Used for the evaluation using CD test disk. Nothing should be connected to PORT2. In case of using optical
connector (TORX176), select “OPT” on JP14(DIR/RX). In case of using RCA connector, select “RX”.
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
JP13
XTE
ADC DIR ADC DIR GND DATA
VD GND
2) Ideal sine wave generated by ROM data
Connect the AKD43XX with PORT2(ADC/ROM). AKD4380 sends MCLK to AKD43XX, and receives LRCK,
BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on
JP12(MCLK) and short JP13(XTE).
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
JP13
XTE
ADC DIR ADC DIR GND DATA
VD GND
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