AK8181B Datasheet, PDF (2/4 Pages) Asahi Kasei Microsystems – AK8181B Evaluation Board

AKD8181B
Power
There are the following three power supplies.
※If you have configured a termination circuit with resistor only (Pattern A or B), it becomes possible to
evaluate even without applying power to the VDD-2V terminal.
- VDD
The core power supply of AK8181B (3.3V)
- VEE
The core power supply of AK8181B (GND)
- VDD-2V
Power supply for the end of the output load resistor (=VDD-2V)
Note) GND of the SMA terminal is connected to the VEE inside the substrate.
Clock input
AK8181B inputs the clock selected by CLK_SEL switch. (External input or crystal)
The clock input signal can terminate at 50Ω if needed. (50Ω is connected to R2 pattern)
Inputs 266MHz or less.
Output load circuit
It can terminate by the following three methods. (Pattern A/B/C)
The state of initial shipment is 【Pattern A】.
【Pattern A】
Q0,1,2,3
Zo=50Ω
Q0N,1N,
2N,3N
Zo=50Ω
※Composition at the time of shipment
0Ω
0.1uF
or Open
RTT
50Ω
NC
50Ω
NC
0Ω
RTT




(V_OH
1
 V_OL ) /(V_CC


2)


2


Z
0
NC：No components
※RTT: 50Ω is mounted at the time of shipment
【Pattern B】
Q0,1,2,3
Zo=50Ω
Q0N,1N,
2N,3N
Zo=50Ω
0Ω
84Ω
short
84Ω
0Ω
125Ω
125Ω
AKD8181B-E-00
2
2012/7