AK4381 Datasheet, PDF (2/21 Pages) Asahi Kasei Microsystems – 108DB 192KHZ 24-BIT 2CH DAC

ASAHI KASEI
n Ordering Guide
AK4381VT
AKD4381
n Pin Layout
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4381
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI
8
Top
View
16
DZFL
15
DZFR
14
VDD
13
VSS
12
AOUTL+
11
AOUTL-
10
AOUTR+
9
AOUTR-
[AK4381]
PIN/FUNCTION
No. Pin Name
I/O Function
1 MCLK
I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK
I Audio Serial Data Clock Pin
3 SDTI
I Audio Serial Data Input Pin
4 LRCK
I L/R Clock Pin
5 PDN
I Power-Down Mode Pin
When at “L”, the AK4381 is in the power-down mode and is held in reset.
The AK4381 should always be reset upon power-up.
6 CSN
I Chip Select Pin
7 CCLK
I Control Data Input Pin
8 CDTI
I Control Data Input Pin in serial mode
9 AOUTR-
O Rch Negative Analog Output Pin
10 AOUTR+
O Rch Positive Analog Output Pin
11 AOUTL-
O Lch Negative Analog Output Pin
12 AOUTL+
O Lch Positive Analog Output Pin
13 VSS
- Ground Pin
14 VDD
- Power Supply Pin
15 DZFR
O Rch Data Zero Input Detect Pin
16 DZFL
O Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
MS0152-E-00
-2-
2002/5