AK4344_10 Datasheet, PDF (19/25 Pages) Asahi Kasei Microsystems – 100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC

[AK4344]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Control 1
1
0
0
0
DIF1 DIF0
PW RSTN
01H Control 2
0
1
0
DFS1 DFS0 DEM1 DEM0 GAIN
02H Control 3
0
0
0
INVL INVR MODE
0
SEL
Notes:
For addresses from 03H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
The bits shown as “0” should be written “0” and the bits shown as “1” should be written “1”.
■ Register Definitions
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Control 1
1
0
0
0
DIF1
DIF0
PW
RSTN
R/W
R/W
Default
1
0
0
0
1
1
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes the click noise occurs. It can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF1-0: Audio data interface formats (Table 3)
Initial: “11”, Mode 3
MS0641-E-01
- 19 -
2010/09