AK4387 Datasheet, PDF (18/21 Pages) Asahi Kasei Microsystems – 106dB 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4387]
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4387) is available in order to allow an
easy study on the layout of a surrounding circuit.
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Mode
Setting
Digital Ground
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 RSTN
6 CSN
7 CCLK
8 CDTI
DZF 16
DVDD 15
AVDD 14
AK4387 ^{VSS 13}
VCOM 12
AOUTL 11
AOUTR 10
NC 9
10
0.1u
0.1u
+ _10u
10u
+
Optional External
Mute Circuits
Analog
Supply 5V
Lch Out
Rch Out
Analog Ground
Figure 9. Typical Connection Diagram (Example 1)
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Mode
Setting
Digital Ground
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 RSTN
6 CSN
7 CCLK
8 CDTI
DZF 16
DVDD 15
AVDD 14
AK4387 ^{VSS 13}
VCOM 12
AOUTL 11
AOUTR 10
NC 9
0.1u ⁺ 10u
10u
+
Optional External
Mute Circuits
Analog
Supply 5V
Lch Out
Rch Out
Analog Ground
Figure 10. Typical Connection Diagram (Example 2)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins should not be left floating.
- THD+N value at 192kHz decreases by around 3dB when using Example 2.
MS0429-E-00
- 18 -
2005/09