AK4706_10 Datasheet, PDF (17/54 Pages) Asahi Kasei Microsystems – 2ch 24bit DAC with AV Switch & HD/SD Video Filter

[AK4706]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=11.4 ∼ 12.6V, VD1=VD2=4.75 ∼ 5.25V, VVD1=VVD2=VVD3=VVD4=4.75 ∼ 5.25V; C_L = 20pF)
Parameter
Symbol
Min
typ
max
Units
Master Clock Frequency 256fs:
fCLK
8.192
12.8
MHz
Duty Cycle
dCLK
40
60
%
384fs:
fCLK
12.288
19.2
MHz
Duty Cycle
dCLK
40
60
%
LRCK Frequency
fs
32
50
kHz
Duty Cycle
Duty
45
55
%
Audio Interface Timing
BICK Period
tBCK
312.5
ns
BICK Pulse Width Low
tBCKL
100
ns
Pulse Width High
tBCKH
100
ns
BICK “↑” to LRCK Edge (Note 19)
tBLR
50
ns
LRCK Edge to BICK “↑” (Note 19)
tLRB
50
ns
SDTI Hold Time
tSDH
50
ns
SDTI Setup Time
tSDS
50
ns
Control Interface Timing (I²C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
fSCL
-
tBUF
1.3
tHD:STA
0.6
400
kHz
-
μs
-
μs
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 20) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
Pulse Width of Spike Noise
tSP
0
50
ns
Suppressed by Input Filter
Reset Timing
PDN Pulse Width
(Note 21)
tPD
150
ns
Note 19. BICK rising edge must not occur at the same time as LRCK edge.
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 21. The AK4706 should be reset by PDN pin = “L” upon power up.
Note 22. I²C-bus is a trademark of NXP B.V.
MS0507-E-01
- 17 -
2010/09