AK4223 Datasheet, PDF (17/27 Pages) Asahi Kasei Microsystems – 6:2 Audio Switch and 6:2 Video Switch

[AK4223]
■ Control Interface
The AK4223 supports the fast-mode I²C-bus system (max: 400kHz).
2-1. WRITE Operation
Figure 13 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010000”. If the slave address matches that of the
AK4223, the AK4223 generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 20). A
R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4223. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 15). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 16). The AK4223 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 19).
The AK4223 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4223
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 8-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 06H prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 21) except for the START and STOP
conditions.
S
T
S
A
R/W = "0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 13. Data Transfer Sequence at the I²C-Bus Mode
0
0
1
0
0
0
0
R/W
Figure 14. The First Byte
0
0
0
0
0
A2
A1
A0
Figure 15. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 16. Byte Structure after the second byte
MS1251-E-00
17
2010/10