AK7757VQ Datasheet, PDF (16/24 Pages) Asahi Kasei Microsystems – 24bit 3ch ADC +4ch DAC + Mic Amp 内蔵 Audio DSP

[AK7757]
■ μP インタフェース(SPI mode)
(Ta= Tmin~Tmax; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V, AVSS=DVSS=0V; CL=20pF)
Parameter
Symbol
min
typ
max
μP Interface Timing (SPI mode)
CSN Fall Time
tWRF
30
CSN Rise Time
tWRR
30
SCLK Fall Time
tSF
30
SCLK Rise Time
tSR
30
SCLK Frequency
fSCLK
2.7
SCLK Low Level Width
tSCLKL
180
SCLK High Level Width
tSCLKH
180
CSN High Level Width
tWRQH
500
From CSN “↑” to IRSTN “↑”
tRST1
600
From IRSTN “↑” to CSN “↓”
tIRRQ
100
From CSN “↓” to SCLK “↓”
tWSC
500
From SCLK “↑” to CSN “↑”
tSCW
800
SI Latch Setup Time
tSIS
180
SI Latch Hold Time
tSIH
180
AK7757 → μP
Delay Time from SCLK “↓”to SO Output
tSOS
180
Hold Time from SCLK “↑” to SO Output (Note 32)
tSOH
180
Note 32. コマンドコードの8bit目入力時は除きます。
Unit
ns
ns
ns
ns
MHz
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
■ μP インタフェース (I²C BUS mode)
(Ta= Tmin~Tmax; AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, AVSS=DVSS=0V; CL=20pF)
Parameter
I²C Timing
Symbol
min
typ max Unit
SCL clock frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
μs
Start Condition Hold Time
(prior to first Clock pulse)
tHD:STA
0.6
μs
Clock Low Time
tLOW
1.3
μs
Clock High Time
tHIGH
0.6
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
μs
SDA Hold Time from SCL Falling
tHD:DAT
0
0.9
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
μs
Rise Time of Both SDA and SCL Lines
tR
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
μs
Pulse Width of Spike Noise Suppressed
by Input Filter
tSP
0
50
ns
Capacitive load on bus
Cb
400
pF
Note 33. I²C-busはNXP B.V.の商標です。
MS1489-J-01-PB
16
2013/05