AK4705 Datasheet, PDF (15/50 Pages) Asahi Kasei Microsystems – 2ch 24bit DAC with AV SCART Switch

SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V)
Parameter
Symbol
Min
typ
Master Clock Frequency 256fs:
fCLK
8.192
Duty Cycle
dCLK
40
384fs:
fCLK
12.288
Duty Cycle
dCLK
40
LRCK Frequency
fs
32
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
tBCK
312.5
BICK Pulse Width Low
tBCKL
100
Pulse Width High
tBCKH
100
BICK “↑” to LRCK Edge (Note: 14)
tBLR
50
LRCK Edge to BICK “↑” (Note: 14)
tLRB
50
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing (I²C Bus):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note: 15) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
Reset Timing
PDN Pulse Width
(Note: 16)
tPD
150
Note: 14. BICK rising edge must not occur at the same time as LRCK edge.
Note: 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 16. The AK4705 should be reset by PDN pin = “L” upon power up.
Note: 17. I²C is a registered trademark of Philips Semiconductors.
[AK4705]
max
Units
12.8
MHz
60
%
19.2
MHz
60
%
50
kHz
55
%
ns
ns
ns
ns
ns
ns
ns
400
kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
50
̽s
400
Ì¿F
ns
MS0451-E-01
- 15 -
2007/06