AK4532_04 Datasheet, PDF (15/17 Pages) Asahi Kasei Microsystems – Internet/Network/General Purpose Multimedia Audio CODEC

ASAHI KASEI
[AK4532]
VCOM pins. All signals, especially clocks, should be kept away from the VRAD and VCOM pins
in order to avoid unwanted coupling into the chip.
3. Analog Inputs
The mixer input and the ADC inputs are single-ended and internally biased to the VCOM voltage with
60kΩ(typ) resistance. The input signal range is typically 2.83Vpp(1Vrms). Figure 3 is an example
for 2Vrms line-level input circuit. The ADC output data format is 2’s complement. The AK4532
accepts input voltages from AGND to VA. The output code is 7FFFH for input above a positive full
scale and 8000H for input below a negative full scale. The ideal code is 0000H with no input signal.
The DC offset is canceled by the internal HPF.
Analog
Input
2Vrms
5.1k
5.1k
0.47u
AK4532
LINE/AUX
Figure 3. 2Vrms Line-level Input
The AK4532 samples the analog inputs at 64fs. The digital filter rejects all noise higher than the stop
band. However, the filter will not reject frequencies right around 64fs(and multiples of 64fs). Most
audio signals do not have significant energy at 64fs. As a result, two 1nF capacitors are necessary
for AINFR and AINFL.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal
range is typically 2.83Vpp(1Vrms). The DAC input data format is 2’s complement. The output
voltage is a positive full scale for 7FFFH and a negative full scale for 8000H. The ideal output is
VCOM voltage for 0000H. The internal switched-capacitor filter and continuous-time filter almost
remove the noise generated by the delta-sigma modulator of DAC beyond the audio passband,
especially low sampling rate. The noise floor level is almost constant and the audible noise level is
-83dB(typ) at 8kHz sampling.
5. Other information
5.1 Clock change
The clock change or LRCK phase shift should be done while muting the DAC output by the master
volume or voice volume to avoid the click noise by out-of-synchronization.
ADC may output digital code at the clock change, or LRCK phase shift may produce incomplete or
destroyed 16bit data. Then some attention is required carefully.
5.2 Offset on mixer inputs
When the mixer gain is set to +12dB, the output has pretty large offset even if the inputs are no signal.
Therefore, large click noise may occur when the gain level is changed quickly.
5.3 Click noise on the analog outputs
The click noise of about -50dB occurs from the analog outputs(LOUT, ROUT) at the power on/off or the
transition of PD register. The analog outputs should be muted externally if the click noise
influences systems application.
0178-E-02
15
2004/12