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AK1542A_17 Datasheet, PDF (15/38 Pages) Asahi Kasei Microsystems – 20 to 600MHz Integer-N Frequency Synthesizer | |||
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[AK1542A]
4.2 Digital Lock Detect
In the digital lock detect, the [LD] pin outputs is âLowâ every time when the frequency is set. And the [LD] pin outputs âHighâ
(which means the locked state) when a phase error smaller than T is detected for N times consecutively. If the phase error
larger than T is detected for N times consecutively when the [LD] pin outputs âHighâ, the [LD] pin outputs âLowâ(which means
the unlocked state).
The threshold counts for lock detection N could be set by D[18:17]={LDCNTSEL[1:0]} in <Address4>.
{LDCNTSEL[1:0]} settings and corresponding counts (N) are as follows:
00: N = 7
01: N = 15
10: N = 31
11: N = 63
The lock detect signal is shown below:
Reference clock
PFD clock
VCO divide clock
Phase detector output
Invalid Valid Invalid
LD output
Valid
Invalid
When âInvalidâ is detected consecutively
for N times, LD outputs âHighâ
Fig. 8 Digital Lock Detect Operations
MS1399-E-02
- 15 -
2014/4
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