AK7752 Datasheet, PDF (14/23 Pages) Asahi Kasei Microsystems – Audio/Hands Free DSP with Stereo CODEC

[AK7752]
2) Reset
(Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Units
INIT_RESET_N
(Note 32)
tRST
600
ns
CK_RESET_N
tRST
600
ns
S_RESET_N
tRST
600
ns
Note 32. The AK7752 can be powered up when INIT_RESET_N pin = “L”. The power supply must be ON and the
master clock must be input before the INIT_RESET_N pin transitions “H”.
3) Audio interface
(Ta=-40°C~85°C; AVDD, DVDD=3.0~3.6V; CL=20pF)
Parameter
Symbol min typ
max
Slave Mode (CKM Mode 2-4)
Delay Time from BITCLK_I “↑” to SYNC_I (Note 33) tBLRD 60
Delay Time from SYNC_I to BITCLK_I “↑” (Note 33) tLRBD 60
Delay Time from SYNC_I,_O to Serial Data Output
tLRD
80
Delay Time from BITCLK_I,_O to Serial Data Output tBSOD
80
Serial Data Output Latch Setup Time
tBSIDS 80
Serial Data Input Latch Hold Time
tBSIDH 80
Master Mode (CKM Mode 0-1)
BITCLK_O Frequency (BIT32FS bit = “0”)
fBCLK
64
BITCLK_O Frequency (BIT32FS bit = “1”)
32
BITCLK_O Duty Factor
50
Delay Time from BITCLK_O “↑” to SYNC_O (Note 34) tBLRD 60
Delay Time from SYNC_O to BITCLK_O “↑” (Note 34) tLRBD 60
Delay Time from SYNC_O to Serial Data Output
tLRD
80
Delay Time from BITCLK_O to Serial Data Output
tBSOD
80
Serial Data Output Latch Setup Time
tBSIDS 80
Serial Data Input Latch Hold Time
tBSIDH 80
Note 33. BITCLK_I “↑“ must not occur at the same time as SYNC_I edge.
Note 34. BITCLK_O “↑“ must not occur at the same time as SYNC_O edge.
(When control register SEL_BCK bit = “0”. The edge reverses when SEL_BCK bit = “1”.)
Units
Ns
Ns
ns
ns
ns
ns
fs
fs
%
ns
ns
ns
ns
Ns
ns
MS0578-E-01-PB
- 14 -
2007/09