AK5385AVF Datasheet, PDF (14/24 Pages) Asahi Kasei Microsystems – 24Bit 192kHz DS ADC

ASAHI KASEI
[AK5385A]
OPERATION OVERVIEW
n System Clock
MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling
frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in Table 2 and LRCK
frequency is selected by DFS1-0 pins as shown in Table 3.
As the AK5385A includes the phase detect circuit for LRCK, the AK5385A is reset automatically when the
synchronization is out of phase by changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided, the
AK5385A may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5385A in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
MCLK
128fs
256fs
384fs
N/A
8.192MHz 12.288MHz
N/A
11.2896MHz 16.9344MHz
N/A
12.288MHz 18.432MHz
N/A
24.576MHz
N/A
24.576MHz
N/A
N/A
Table 1. System Clock Example
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
CKS1 pin CKS0 pin MCLK Frequency
L
L
256fs
L
H
128fs
H
L
512fs
H
H
384fs
Table 2. MCLK Frequency
DFS1 pin
L
L
H
H
DFS0 pin
LRCK Frequency
L
8kHz ≤ fs ≤ 54kHz
H
54kHz < fs ≤ 108kHz
L
108kHz < fs ≤ 216kHz
H
N/A
Table 3. Sampling Speed
When changing MCLK frequency in master/slave mode, the AK5385A should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) to 24.576MHz(@fs=96kHz) at CKS1 pin = CKS0 pin = “L”.
If the CKS1-0 and DFS1-0 pins are changed with same MCLK frequency in master/slave mode (ex. MCLK is fixed to
24.576MHz and fs is changed from 48kHz (CKS1 pin = “L”, CKS0 pin = “L”) to 96kHz (CKS1 pin = “L”, CKS0 pin =
“H”)), no reset by PDN pin = “L” is required.
MS0265-E-01
- 14 -
2003/11