AK5371A Datasheet, PDF (14/32 Pages) Asahi Kasei Microsystems – 2ch A/D Converter with USB I/F

ASAHI KASEI
[AK5371A]
„ System Block Diagram
The following figure shows the system connection diagram. This is an example which uses external 1K bit EEPROM (AK93C45A)
as Device and String Descriptor. If EEPROM is not used, EPEN pin should be tied to VSS1.
Ceramic capacitors (0.1uF) for VA pin, VD pin, VREF pin and VCOM pin should be located as near as possible.
<REMARK> This drawing does NOT mean physical pin locations/ordering
R1:4.7k
10Ω 10uH
0.1u
10u
Regulator
0.1u 100u
0.1u 4.7u 0.1u 4.7u ^0.1u
4.7u
0.1u
4.7u
0.1u
R1:4.7k
R0
VREF VCOM
MICBIAS
VA VSS3 VSS2 VD VSS1
RSTN
0.1u 100u
C1:1.0u<
C2:0.33u
C1:1.0u<
Phone Jack
STEREO SW _C2:0.33u
MICR
AMPR1O
AMPR2I
MICL
AMPL1O
AMPL2I
AMP2RO AMP2LO
CS
SK
EPAO
EPDI
Testmode 1
Testmode 2
Testmode 3
Test
DP
DN
LFLT1,2 XTALOUT XTALIN
56k
10u
3300p
EEPROM
1.5k
D+
D-
To Host/Hub
51k
C3:1000p C3:1000p 8200p
1M
18k
11.2896M
6800p Cd Cd
5V
GND
GND
VSS3
VSS1
C1 is specified for lower end cut-off frequency
C3 forms Anti-aliasing filter in conjuction with the internal resistor at AMPR2O/AMPL2O
R0: 0Ω resister when BIASSEL is Low. 330Ω resister when BIASSEL is High
Cd: Please select the appropriate value according to crystal resonator’s characteristics
MS0546-E-00
MS0103-E-00
14
2007/02