AK4384 Datasheet, PDF (14/22 Pages) Asahi Kasei Microsystems – 106dB 192kHz 24-Bit 2ch DAC

ASAHI KASEI
[AK4384]
n System Reset
The AK4384 should be reset once by bringing PDN= “L” upon power-up. The AK4384 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4384 is in the power-down
mode until MCLK and LRCK are input.
n Power-down
The AK4384 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, LRCK, BICK
Normal Operation
Power-down
“0” data
GD (1)
(3) (2)
(4)
Don’t care
DZFL/DZFR
(6)
External
MUTE
(5)
Mute ON
Normal Operation
GD (1)
(3)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
MS0176-E-00
- 14 -
2002/09