AK9822 Datasheet, PDF (13/17 Pages) Asahi Kasei Microsystems – 2K / 4Kbit EEPROM with 2ch 8bit D/A Converter

ASAHI KASEI
[AK9822/24]
„ AC characteristics
1)EEPROM section
(VCC=+1.8V∼5.5V, GND=0V, Ta=-40∼+85°C unless otherwise specified )
Parameter
SK cycle
SK pulse width
Symbol
Conditions
min
tSKP1 (note6),(note7)
500
tSKP2 (note8)
1.5
tSKW1 (note6),(note7)
250
tSKW2 (note8)
750
max
Units
ns
us
ns
ns
SK pulse high level width
tSKH1 (note6)
250
ns
(note10)
tSKH2 (note7)
500
ns
tSKH3 (note8)
750
ns
CS setup time
tCSS
100
ns
CS hold time
tCSH1 READ
100
ns
WREN, WRDS
PDEN, PDDS
tCSH2 CALL
2
us
WRITE (note9)
SK setup time
tSKS
100
ns
Data setup time
tDIS1 (note6)
100
ns
tDIS2 (note7)
150
ns
tDIS3 (note8)
200
ns
data hold time
tDIH1 (note6)
100
ns
tDIH2 (note7)
150
ns
tDIH3 (note8)
200
ns
DO pin output delay
(note11), (note13)
tPD1
tPD2
tPD3
(note6)
(note7)
(note8)
150
ns
250
ns
500
ns
Selftimed program time
tE/W
10
ms
Write recovery time
tRC
100
ns
Min. CS high time (note12) tCS
250
ns
DO pin high-Z time
tOZ
500
ns
note6. 4.0V≤VCC≤5.5V
note7. 2.5V≤VCC<4.0V
note8. 1.8V≤VCC<2.5V
note9. In case of the following case, tCSH is min.100ns.
• The WRITE instruction by which the address "0" is specified is executed at the WRITE
enable state.
• The WRITE instruction by which the address "1∼127/255" is specified is executed.
note10. The tSKH is the high pulse width of 16th SK pulse in READ operation. When the
data in the next address are read sequentially by continuing to provide clock, tSKH are
applied to the high pulse width of 32nd and 48th (multiple of 16) SK pulse in READ
operation.
note11. In case that Ready/Busy signal output, tPD is min.1us.
note12. The first CS high time is the tACS after Vcc is applied to the part.
note13. CL=100pF
DAD01E-00
- 13 -
1999/05