AK5357_09 Datasheet, PDF (13/20 Pages) Asahi Kasei Microsystems – 24Bit 96kHz ΔΣ ADC

[AK5357]
■ Power down
The AK5357 is placed in the power-down mode by bringing the PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be executed after power-up. In the power-down mode, the VCOM is the same voltage as
AGND. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO
becomes available after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During
initialization, the ADC digital output data of both channels are forced to a 2’s complement “0”. The ADC outputs settle in
the value corresponding to the input signals after the initialization was completed (Settling approximately takes the group
delay time).
PDN
Internal
State
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
Normal Operation
GD ₍₂₎
Power-down
Idle Noise
(3)
“0”data
(4)
(1)
Initialize
Normal Operation
GD
“0”data
Idle Noise
Notes:
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D output is “0” data at the power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5357 should be in the power-down state.
Figure 3. Power-down/up sequence example
■ System Reset
The AK5357 should be reset once by bringing the PDN pin “L” after power-up. In slave mode, the internal timing starts
clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5357 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input.
MS0294-E-03
- 13 -
2009/03