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AK4430ET Datasheet, PDF (12/18 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo
[AK4430]
■ System Reset
The AK4430 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4430 is in power-down mode until LRCK are input.
Power Supply
(VDD, CVDD)
(5)
MCLK
Low
Analog
Circuit
Power down
20 us
(1)
Digital
Circuit
Charge Pump
Circuit
Power down
(2)
Power down
Charge Pump
Counter circuit
Power-up
2, 3
LRCK
Power-up
Power-up
(3)
Time A
D/A In
(Digital)
“0” data
D/A Out
(Analog)
MUTE (D/A Out)
(4)
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A =176/fs: Normal speed mode
Time A =352/fs: Double speed mode
Time A =704/fs: Quad speed mode
(4) No audible click noise occurs under normal conditions.
(5) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at different time from this figure.
Figure 8. System Reset Diagram
MS1196-E-01
- 12 -
2011/03