AK4319A Datasheet, PDF (12/18 Pages) Asahi Kasei Microsystems – 18Bit SCF DAC

ASAHI KASEI
„ Power-Down
[AK4319A]
The AK4319A are placed in the power-down mode by bringing PD pin "L" and the analog outputs are
floating(Hi-Z). Figure 7 shows an example of the system timing at the power-down and power-up.
{¹ Analog output has the group delay(GD).
{² When power-down is initiated, analog outputs are set into Hi-Z. Output noise level is about
-110dB.
{³ Some -50dB of click noise occurs at the transition("↑↓") of PD pin.
{⁴ When the master clock is stopped, the AK4319A should have been in the power-down mode.
{⁵ If the click noise({³ )is a problem, an external mute circuit which generates above timing ({⁵ )is
needed. Please refer to Figure 7 .
Figure 7 . Power-down/up sequence example
„ System Reset
The AK4319A should be reset once by bringing PD "L" upon power-up. The AK4319A is powered up and
the internal timing starts clocking by LRCK "↑" after exiting reset and power down state by XTI. The
AK4319A is in power-down mode until LRCK is input.
„ External mute circuit
Some click noise may occur at the transition("↑↓") of PD signal. The click noise of PD signal can be
avoided by controlling the external mute circuit. The S/N of -110dB could be achieved by muting the
analog outputs using DZF signal.
M0011-E-01
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1998/6