AK5358 Datasheet, PDF (11/17 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC

ASAHI KASEI
[AK5358]
OPERATION OVERVIEW
„ System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5358 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5358 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
8.192MHz 12.288MHz 16.384MHz
11.2896MHz 16.9344MHz 22.5792MHz
12.288MHz 18.432MHz 24.576MHz
24.576MHz 36.864MHz
N/A
Table 1. System Clock Example
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
Mode
0
1
2
3
4
5
6
7
CKS2
L
L
L
L
H
H
H
H
CKS1
L
L
H
H
L
L
H
H
CKS0
L
H
L
H
L
H
L
H
Input Level Master/Slave
MCLK
CMOS
Slave
256/384fs (8k≤fs≤96k)
512/768fs (8k≤fs≤48k)
Reserved
CMOS
Master
256fs (8k≤fs≤96k)
CMOS
Master
512fs (8k≤fs≤48k)
Reserved
Reserved
CMOS
Master
384fs (8k≤fs≤96k)
CMOS
Master
768fs (8k≤fs≤48k)
Table 2. Operation Mode Select
Note 13. SDTO outputs 16bit data at SCLK=32fs.
SCLK
≥ 48fs or 32fs
(Note 13)
64fs
64fs
64fs
64fs
MS0438-E-00
- 11 -
2005/11