AK4647VQ Datasheet, PDF (11/72 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4647]
DCಛੑ

(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
min
typ
Max
Units
High-Level Input Voltage 2.2V≤DVDD≤3.6V
VIH 70%DVDD
-
-
V
Low-Level Input Voltage 2.2V≤DVDD≤3.6V
VIH
-
-
30%DVDD V
High-Level Output Voltage
(Iout=−200μA) VOH DVDD−0.2
-
Low-Level Output Voltage
(Except SDA pin: Iout=200μA) VOL
-
-
(SDA pin: Iout=3mA) VOL
-
-
-
V
0.2
V
0.4
V
Input Leakage Current
Iin
-
-
±10
μA
εΠονϯάಛੑ
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Output Timing
Frequency
fs
Duty Cycle
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
11.2896
0.4/fCLK
0.4/fCLK
0.2352
40
-
7.35
-
-
-
-
-
-
-
-
50
33
-
50
1/(32fs)
1/(64fs)
50
27
-
-
12.288
60
-
48
-
-
-
-
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
Pulse Width Low
tCLKL 0.4/fCLK
-
Pulse Width High
tCLKH 0.4/fCLK
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
LRCK Input Timing
Frequency
fs
7.35
-
Duty
Duty
45
-
BICK Input Timing
Period
tBCK
1/(64fs)
-
Pulse Width Low
tBCKL 0.4 x tBCK
-
Pulse Width High
tBCKH 0.4 x tBCK
-
27
-
-
12.288
60
-
48
55
1/(32fs)
-
-
Units
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
%
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
ns
MS0566-J-00
- 11 -
2006/11