AK2331 Datasheet, PDF (11/17 Pages) Asahi Kasei Microsystems – DAC Type 8-bit 4-channel Electronic Volume

[AK2331]
Digital AC Timing
Serial interface timing
The AK2331 writes data via the three-wire synchronous serial interface by means of CSN, SCLK,
and SDATA.
SDATA (serial data) consists of a register address (starting from the MSB, A3 to A0) and control
data (starting from the MSB, D7 to D0).
<1> CSN (chip select) is normally set to the high level.
When CSN is set to the low level, the serial interface becomes active.
<2> When a write operation is performed, an address and data are input in synchronization with the
rising edges of 12 SCLK clock pulses while CSN is low.
<3> A write setting is made on the assumption that 12 clock pulses are input from SCLK while CSN is
low.
Note that if clock pulses more than or less than 12 clock pulses are input, data cannot be set
correctly.
CSN
SCLK
SDATA
tCSS
tWH
tWL
tCSLH
tDS
tDH
A3
A2
A1 A0
D7
D6
D1 D0
tCSHH
Rising and falling times
SCLK
Parameter
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
CSN low hold time
CSN high hold time
DAC output setting
time
SCLK rising time
SCLK falling time
t_R
t_F
VIH
VIL
Symbol
Condition
Min. Typ. Max. Unit
t_CSS
t_DS
t_DH
t_WH
t_WL
t_CSLH
t_CSHH
100
ns
100
ns
100
ns
500
ns
500
ns
100
ns
100
ns
VOUT[7:0]=
0x10↔0xEF
Until output reaches
t_LDD
the half LSB of the final
value.
300
μs
RS=2.2kΩ,
L=22kΩ,
CL=1000pF
t_R
100
ns
t_F
100
ns
Note Digital input timing measurements are made at 0.5DVDD for rising and falling edges.
MS0903-E-00
- 11 -
2008/03