AKD4631 Datasheet, PDF (10/43 Pages) Asahi Kasei Microsystems – AK4631-VN Evaluation board Rev.0

ASAHI KASEI
[AKD4631-VN]
„ Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated.
: Common. (The connector “DGND” can be open.) <Default>
2. JP2 (AIN)
OPEN
SHORT
: Connection between MICOUT pin and AIN pin of the AK4631VN.
: No connection.
: Connection. <Default>
3. JP3 (AVDD_SEL) : AVDD of the AK4631VN
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
4. JP9 (DVDD_SEL) : DVDD of the AK4631VN
AVDD
: DVDD is supplied from “AVDD”. < Default >
DVDD
: DVDD is supplied from “DVDD ” jack.
5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
: Logic block of LVC is supplied from “DVDD”. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
6. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
: Logic is supplied from supply line of LVC. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
7. JP4 (SVDD_SEL) : SVDD of the AK4631VN
REG
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
SVDD
: SVDD is supplied from “SVDD ” jack.
8. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1 : The check from MCKO1 of AK4114 is provided to MCKI of the AK4631VN. < Default >
MCKO2 : The check from MCKO2 of AK4114 is provided to MCKI of the AK4631VN.
<KM077301>
- 10 -
2005/01