AK5483 Datasheet, PDF (10/14 Pages) Asahi Kasei Microsystems – 10Bit 20MHz 3CH A/D Converter

ASAHI KASEI
[AK5483]
Theory of operation
* Analog Input Range
External Reference Voltage fed through VTP/VBT determine the analog input range of all
three channels of 10 Bit AD converter.
The Zero level of analog input(AINA,AINB,AINC) is VBT and the Full Scale is VTP.
* Converted Digital Output Code
The converted Digital Output Code is Straight Binary format.
For Zero Scale(AIN=VBT), the output code is all zero.
For Full Scale(AIN=VTP), the output code is all one.
The deviation from these ideal voltage is expressed by Offset[EOB,EOT].
* Sampling Frequency Select
Reduction of power consumption is realized for sampling frequency less than 15MHz.
20MHz mode : SEL=High Normal current is consumed to operate at Fc=20MHz.
15MHz mode ] : SEL=Low Current is reduced with restriction of Fcmax=15MHz.
* Chip Enable Function
By setting CEN=High, whole chip of AK5483 powers down.
Under the power down state, all digital output are High-Impedance and Vref related
circuit also powers down.
The internal reference voltage is generated with input of CEN=LOW & supply of external
VREF voltage. Depending on the state of external capacitors, some period is required to
charge them.
* CKI,Pipeline delay,Data Output Timing
Feed A/D converter sampling clock through CKI pin.
Rising edges of CKI track and hold the analog input signal.
After 6clock pipeline delay, 10 bit digital output code is obtained.
* Caution for Power Supply
It is recommended to supply both AVDD and DVDD supply from single regulator.
(Please observe absolute maximum rating spec. DVDD<=(AVDD+0.3V) even at the start-up
sequence of the power.)
M0035-E-01
- 10 -
1999/03