AK4145 Datasheet, PDF (10/27 Pages) Asahi Kasei Microsystems – Digital BTSC Stereo Encoder

[AK4145]
■ Power-on Sequence
After setting the PDN pin “L” to “H”, the AK4145 remains in power-down mode until a LRCK rising edge after MCLK.
When the MCLK and LRCK are provided, the AK4145 exits reset state, power-on the voltage reference circuit, and the
PLL will be locked. The output signal is masked until when the PLL locks to the MCLK (also RSTN bit = “1” is required
in serial mode).
Power off
AVDD
TVDD
AVDD
PDN (I)
Power on
MC LK (I)
LRCK (I)
(PLL: Internal)
(PLL Lock : Internal)
CA (O)
···
(1)
CA=VCOM=VSS
(2)
CA=VC OM≅AVDD/2
(3)
Normal Operat ion
Pow er-down state
(1) Waiting the MCLK &L RCK . PLL=free run
(2) PLL Locking Time
(3) Data output is Muted
Figure 5. Power-on Sequence
Note:
When changing the sampling rate, the PLL lock signal and BTSC encoder are initialized. The output is muted until the
PLL re-locks.
■ System Clock
The external clocks required to operate the AK4145 are MCLK, LRCK and BICK. The AK4145 supports 256fs, 384fs,
512fs and 768fs as master clock (MCLK). The AK4145 should be reset by the PDN pin = “L” after these clocks are
provided. After exiting reset by the PDN pin = “H”, the AK4145 remains in power-down mode until a LRCK rising edge
after MCLK.
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
768fs
12.2880MHz 16.3840MHz 24.576MHz
16.9344MHz 22.5792MHz 33.8688MHz
18.4320MHz 24.5760MHz 36.8640MHz
Table 4. System clock example
BICK
64fs
128fs
2.0480MHz 4.0960MHz
2.8224MHz 5.6448MHz
3.0720MHz 6.1440MHz
MS0982-E-01
- 10 -
2010/09