AK2308LV_05 Datasheet, PDF (10/31 Pages) Asahi Kasei Microsystems – SPEECH CODEC for Digital Key telephone

ASAHI KASEI
2-2 Timing and format of the PCM interface
[AK2308LV]
2-2-1 u/A-Law PCM data Mode
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.
Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2308LV occupies
the first time slot as is indicated in figures below.
2-2-1-a Signals
- Frame Sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal
clock of the LSI is generated based o n this FS signal.
- Bit Clock (BCLK)
BCLK defines the PCM data rate. BCLK can be varied from 64kHz to 2.048MHz by 64kHz step.
- PCM data output (DX)
DX is an output signal of 64Kbps PCM u/A -law data. The data is synchronized to the BCLK which determ ines the data
rate. In the period in which the PCM data is not occupied, the DX pin turns to Hi -impedance. In the long frame mode, the
LSB bit turns to Hi-impedance at the faster edge of either FS falling edge or 9 ^th rising edge of BCLK.
- PCM data input (DR)
DR is an input signal of 64Kbps PCM u/A -law data. The data is clocked by the falling edge of the BCLK and fed into the
D/A block.
2-2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection
AK2308LV monitors the duration of the “H” level of FS and automatically selects LF or SF interface format.
Period of FS=”H”
More than 2 clocks of BCLK
1 clock of BCLK
Interface format
LF
SF
2-2-1-c Frame format of the interface
Long Frame format
FS
BCLK
M o re th an 2 clo cks
1 25 us(8K H z)
DX
7
6
5
4
3
2
10
DR
D o n ’t
c a re
7
6
5
4
3
2
10
D o n ’t c a re
Short Frame format
FS
BCLK
DX
DR
D on’t
care
125us(8KHz)
7 6 5 4 3 2 10
76543210
D on’t care
Notice FS must be 8kHz clock that is synchronized with BCLK.
MS0227-E-01
10
2005/12