AIC2822 Datasheet, PDF (8/9 Pages) Analog Intergrations Corporation – 2A 23V Synchronous PWM Step-Down Converter

AIC2822
ΔV_OUT
=
ΔI_L
8 × f_OSC × C3
+ ESR
ΔI_L
For lower output voltage ripple, the use of low ESR
ceramic capacitor is recommended. The tantalum
capacitor can also be used well, but its ERS is larger
than that of ceramic capacitor.
When choosing the input and output ceramic
capacitors, X5R and X7R types are recommended
because they retain their capacitance over wider
ranges of voltage and temperature than other types.
Loop Compensation
The system may have another zero of importance, if
the output capacitor has a large capacitance and/or a
high ESR value. The zero, due to the ESR and capaci-
tance of the output capacitor, is located at:
1
F_ESR = _{2π × C3 × RESR}
In this case, a third pole set by the compensation ca-
pacitor, C7 and the compensation resistor, Rc is used
to compensate the effect of the ESR zero on the loop
gain. This pole is located at:
1
F_P2 = _{2π × C7 × Rc}
※ The values of the compensation components are
given in the AIC2822 demo board user manual.
In order to avoid the poor output voltage ripple and low
efficiency caused by instability, AIC2822 requires a
proper external compensation network to compensate
its feedback loop. In this external compensation
network, the compensation resistor, R_C, and the
compensation capacitor, C_C, are used to set the high-
frequency integrator gain and the integrator zero. C7 is
used to cancel the zero caused by the output capacitor
and it’s ESR. While using the ceramic capacitor as the
output capacitor, C7 can be omitted due to the small
ESR.
The system has one pole of importance, due to the
output capacitor, C3 and the load resistor. This poles
is located at:
1
F_P1 = _{2π × C3 × RLOAD}
The system has one zero of importance, due to the
compensation capacitor, Cc and the compensation
resistor, Rc. This zero is located at:
1
F_Z1 = _{2π × Cc × Rc}
Layout Consideration
In order to ensure a proper operation of AIC2822, the
following points should be managed comprehensively.
1. The input capacitor and V_IN should be placed as
close as possible to each other to reduce the input
voltage ripple and noise.
2. The output loop, which is consisted of the inductor,
the internal power switch, the Schottky diode and
the output capacitor, should be kept as small as
possible.
3. The routes with large current should be kept short
and wide.
4. Logically the large current on the converter should
flow at the same direction.
5. In order to prevent the effect from noise, the IC’s
GND pin should be placed close to the ground of
the input bypass capacitor.
6. The FB pin should be connected to the feedback
resistors directly and the route should be away
from the noise sources.
8