AIC1570 Datasheet, PDF (10/18 Pages) Analog Intergrations Corporation – 5-bit DAC, Synchronous PWM Power Regulator with LDO and Linear Controller

AIC1570
Pin 21: PGND:
Driver power GND pin. PGND
should be connected to a low
impedance ground plane in
close to lower N-MOSFET
source.
Pin 22: LGATE: Lower N-MOSFET gate drive
pin.
Pin 23: PHASE: Over-current detection pin.
Connect the PHASE pin to
DESCRIPTION
The AIC1570 is designed for microprocessor
computer applications with 3.3V and 5V power,
and 12V bias input. This IC has one PWM
controller, a linear regulator, and a linear controller.
The PWM controller is designed to regulate the
microprocessor core voltage (V_OUT1) by driving 2
MOSFETs (Q1 and Q2) in a synchronous rectified
buck converter configuration. The core voltage is
regulated to a level programmed by the 5 bit D/A
converter. An integrated linear regulator supplies
the 2.5V clock power (V_OUT2). The linear controller
drive an external MOSFET(Q3) to supply the GTL
bus power(V_OUT3)
The Power-On Reset (POR) function continually
monitors the input supply voltage +12V at VCC pin,
the 5V input voltage at OCSET pin, and the 3.3V
input at VIN2 pin. The POR function initiates soft-
start operation after all three input supply voltage
exceed their POR thresholds.
Soft-Start
The POR function initiates the soft-start sequence.
Initially, the voltage on SS pin rapidly increases to
approximate 1V. Then an internal 10µA current
source charges an external capacitor (C_SS) on the
SS pin to 4V. As the SS pin voltage slews from 1V
to 4V, the PWM error amplifier reference input
(Non-inverting terminal) and output (COMP1 pin)
is clamped to a level proportional to the SS pin
voltage. As the SS pin voltage slew from 1V to 4V,
source of the external high-side
N-MOSFET. This pin detects the
voltage drop across the high-
side N-MOSFET R_DS(ON) for over-
current protection.
Pin 24: UGATE: External high-side N-MOSFET
gate drive pin. Connect UGATE
to gate of the external high-side
N-MOSFET.
the output clamp generates PHASE pulses of
increasing width that charge the output capacitors.
Additionally both linear regulators’ reference inputs
are clamped to a voltage proportional to the SS pin
voltage. This method provides a controlled output
voltage smooth rise.
Fig.4 and Fig.5 show the soft-start sequence for
the typical application. The internal oscillator’s
triangular waveform is compared to the clamped
error amplifier output voltage. As the SS pin
voltage increases, the pulse width on PHASE pin
increases. The interval of increasing pulse width
continues until output reaches sufficient voltage to
transfer control to the input reference clamp.
Each linear output (VOUT2 and VOUT3) initially
follows a ramp. When each output reaches
sufficient voltage the input reference clamp slows
the rate of output voltage rise. The PGOOD signal
toggles ‘high’ when all output voltage levels have
exceeded their under-voltage levels.
Fault Protection
All three outputs are monitored and protected
against extreme overload. A sustained overload
on any output or over-voltage on PWM output
disable all converters and drive the FAULT pin to
VCC.
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