AN019 Datasheet, PDF (1/6 Pages) Analog Intergrations Corporation – Ripple Noise of LDO

AN019
A Better Approach of Dealing with Ripple Noise of LDO
Introduction
It has been a trend that cellular phones, audio
systems, cordless phones and portable appliances
have a requirement for low noise power supplies. We
are talking about an interesting subject how to control
input noise caused by external disturbance and
reduce output noise of LDO to provide power with
lower noise for logic IC.
power line and capacitors may improve the noise
problem.
Besides, most of the LDO are featured with ripple
rejection function to reduce the noise. Such as
AIC1730, it can get lower output noise due to high
ripple rejection and bypass polarity of IC. The
followings describe details about inductor effect on
power line and LDO ripple rejection function.
In general, the ripple noise of LDO power line will be
influenced by a fast charge/discharge on capacitors
out of the external switch converter and to LDO at
input polarity, respectively. The power source of LDO
is originally from the output of the converter. And the
output is influenced by the ringing of current, which is
caused by the rising and falling of edges of the switch
MOSFET, on power line. It is a serious problem to
generate noise and false signals at input polarity of
LDO from power line. In order to avoid the problem,
we employ some bypass capacitors or put the input
capacitor as close as possible to the input polarity of
LDO. In a high-speed environment, the inductive
effect on power line and the input capacitor become
very critical. The output polarity of high-speed switch
generates high frequency noise on the power line.
And the ringing makes LDO input capacitor with high
lead inductor as an open circuit. The open circuit
prevents the power line, flowing with current, from
ripple noise on input polarity, high noises on output
polarity and false signals on logic IC to maintain the
system at a stable state. Conclusively, adding bypass
capacitors (MLCC) or reducing inductor effect on
July 2001
The influence of inductor effect over LDO
u Formula of inductor effect on power line
l
LDO
V_IN
+
3 ^VIN
VOUT
2
C_IN
d
1 ^GND
GND
V_OUT
+
C_OUT
Figure 1: Inductor Effect on Power Line
Most of the printed circuit boards are designed to
maintain short distances from C_IN to the input polarity
of IC as well as from power to ground. As a result,
users may reduce the inductor effect on power line
and lead inductor of capacitor. In addition, LDO has
better reliable system due to a low-impedance path
when bypass capacitor considered. As shown in
figure1, the input capacitor is charged to prevent V_IN
drop. Therefore, distance between C_IN and input
polarity is a crucial point. The inductor will disturb
power line when IC works normally. The inductor
1