AN014 Datasheet, PDF (1/6 Pages) Analog Intergrations Corporation – Implement 3.3Vdual using AIC1730

AN014
Implement 3.3Vdual using AIC1730 for DRAM
Supply on IAPC Motherboard
Introduction
Today, PCs need to remain constantly connected to
the outside world, but at the same time consume
minimum power. Even looking “idle”, it is still
possible to receive a message from the Internet, an
incoming fax, or a phone call. The PC must wake up
from “sleep” mode to “on” mode automatically, that is,
to be an Instantly Available PC (IAPC)
The “Advanced Configuration and Power Interface”,
or ACPI, is a system for controlling the use of power
in a computer. It enables the computer manufacturer
and the computer user to determine the computer
power usage dynamically.
As the ACPI specified, there are 3 ACPI states that
are of primary concerns to the system designer,
designated S0, S3 and S5. S0 is the full-power state,
the state of the computer when it is being actively
used. The other two states are sleep states,
reflecting differing levels of power-down.
S3 and S5
S3 is a state in which the processor is powered
down, but its last state is reserved in IC memory,
which is kept on. Since access speed of memory is
fast, the computer can quickly come back up to full
operation. However, this state continues to draw
moderate power, due to the memory, which has
been kept alive and also called STR (Suspend to
RAM).
S5 is a state in which memory is off, and the last
state of the processor has been written to the hard
disk. Since the access time of disk is slow, the
computer takes longer time to come back to full
operation. However, since memory is off, this state
draws minimal power.
Operation Description
The 3.3V SDRAM output is intended to provide
power to SDRAM memory. Most system will use this
power. The 3.3V SDRAM is generated by either one
of the two sources, which are +3.3V main and linear
regulator from +5V standby, as shown in Figure 1.
When main power is present, the MOSFET Q1 is
turned on as a switch. That makes input and output
connected. When the main power is absent, the
linear regulator is activated and generating a
regulated 3 3V from +5V standby. The MOSFET Q1
must be connected as shown in the figure to avoid
back-feed.
Aug 2000
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