TMUX03155 Datasheet, PDF (7/120 Pages) Agere Systems – TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Data Sheet
April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Description (continued)
Automatic receive monitoring functions can be config-
ured to provide an interrupt to the control system, or
the device can be operated in a polled mode.
Built-in loopback at both the STS-1/AU-3 and STS-3/
STM-1 (AU-4) interfaces provides maximum flexibility
for use in a number of SONET/SDH products including
path termination multiplexers, add/drop multiplexers,
and digital cross connects.
A high-speed microprocessor interface and full user
programmability on STS-1/AU-3 to STS-3/STM-1 (AU-
4) slot insertion and drop provide maximum flexibility
for I/O configuration.
Nomenclature Assumptions
Throughout this document, certain assumptions are
made about nomenclature. The transmission path that
outputs the STS-3/STM-1 (AU-4) signal is called the
transmit direction, while the transmission path that
receives the STS-3/STM-1 (AU-4) signal is referred to
as the receive path. The low-speed (LS) side of the
device transmits or receives the STS-1/AU-3 signals,
while the high-speed (HS) side of the device transmits
or receives the STS-3/STM-1 (AU-4) signal.
The LSB (least significant bit) of a byte is labeled 0 and
the MSB (most significant bit) is labeled N – 1, where N
is the total number of bits in the word. A signal that
ends in [3—1][7:0] implies there are three separate sig-
nals, each containing 8 bits.
A control bit that has only one function causes that
function to be active when the control bit is set to a
logic 1. For example, setting RLSCLKINV, 0x57 to a
logic 1 causes the low-speed output clock to be
inverted. A control bit with two names performs the first
choice when set to a logic 0 and the second choice
when set to a logic 1. For example, TSONET_SDH,
0x34 when set to a logic 0 puts the transmit direction in
the SONET mode and when set to a logic 1 puts the
transmit direction in SDH mode.
Where necessary to avoid confusion, numbers may be
expressed using a format to specify their base. The fol-
lowing are examples:
I 9\D = 9 decimal.
I 0x04 = 04 hexadecimal.
I 11\B = 11 binary.
Block Diagram
In the transmit direction, the device outputs a clock and
sync and accepts bused data [7:0] and a parity signal
from up to three devices. The device outputs one data
bundle at the STS-3/STM-1 (AU-4) rate (clock, sync,
data [7:0], and parity bit). A local clock and optional
frame sync signal are needed for operation of the
device. A transport overhead access channel (TOAC)
is provided to allow overwriting of the transport over-
head bytes in the output STS-3/STM-1 (AU-4) frame.
In the receive direction, the device accepts one STS-3/
STM-1 (AU-4) bundle (clock, data, parity). Optional
clock and data recovery is available on the STS-3/
STM-1 (AU-4) receive input. The device also accepts a
loss-of-signal indication from an external source. The
device outputs three STS-1/AU-3 signals over a bus
interface (clock, data, J0 time, parity). The STS-3/STM-
1 (AU-4) input clock is used to clock this direction. A
transport overhead access channel is provided for
additional external monitoring of the incoming transport
overhead of the STS-3/STM-1 (AU-4) frame. A pointer
interpreter is provided to monitor path functions.
The device also has loopback capabilities at the STS-
1/AU-3 and STS-3/STM-1 (AU-4) interfaces. In addi-
tion, the device supports STS-1 termination. An 8-bit
microprocessor interface, JTAG control logic, and in-
circuit test capabilities are also provided.
Agere Systems Inc.
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