ORT8850 Datasheet, PDF (61/112 Pages) Agere Systems – Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Data Sheet
August 2001
ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Input/Output Buffer Measurement Conditions (on-LVDS Buffer)
VCC GND
TO THE OUTPUT UNDER TEST
50 pF
TO THE OUTPUT UNDER TEST
1 kΩ
50 pF
A. Load Used to Measure Propagation Delay
B. Load Used to Measure Rising/Falling Edges
Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.
5-3234(F)
Figure 19. ac Test Loads
out[i]
ts[i]
PAD
OUT
ac TEST LOADS (SHOWN ABOVE)
VDD
out[i] VDD/2
VSS
PAD
OUT
1.5 V
0.0 V
TPHH
TPLL
Figure 20. Output Buffer Delays
5-3233.a(F)
Agere Systems Inc.
PAD
IN
in[i]
3.0 V
PAD IN 1.5 V
0.0 V
VDD
in[i] VDD/2
VSS
TPHH
TPLL
Figure 21. Input Buffer Delays
5-3235(F)
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