TTSI4K32T Datasheet, PDF (42/64 Pages) Agere Systems – 4096-Channel, 32-Highway Time-Slot Interchanger

TTSI4K32T
4096-Channel, 32-Highway Time-Slot Interchanger
Data Sheet
June 2000
Configuration Register Architecture (continued)
Table 22. Test Command Register (0x09)
Bit
7
6
5—4
3—2
1—0
Symbol
STTPG
STTPC
GENHDR
[1—0]
CHKHDR
[1—0]
—
Name/Description
Start Test-Pattern Generator. Writing a 1 to this register will cause the genera-
tor to start generating a test pattern based on the pattern indicated in the test-
pattern style register. Writing a 0 to this register will stop the test-pattern genera-
tion and provide the opportunity to change the test-pattern style.
Start Test-Pattern Checker. Writing a 1 to this register will cause the checker to
start locking on to a test pattern based on the pattern indicated in the test-
pattern style register. Writing a 0 to this register will stop the test-pattern check-
ing and provide the opportunity to change the test-pattern style.
Test-Pattern Generator Highway Data Rate. These bits are used to indicate
the highway data rate of the transmit highway selected for test-pattern genera-
tion. It must match the Tx highway data rate which was set in transmit highway
configuration register (byte 2), HDR[1—0] bits. The transmit highway selection
for test-pattern generation is done using the connection store. Only one highway
at a time can be involved with test-pattern generation. Test-pattern generation
and checking does not affect the operation of other time slots or highways.
GENHDR1
0
0
1
1
GENHDR0
0
1
0
1
2.048 Mbits/s (default)
4.096 Mbits/s
8.192 Mbits/s
0.000 Mbits/s (idle, not transmitting data)
Test-Pattern Checker Highway Data Rate. These bits are used to indicate the
highway data rate of the receive highway selected for test-pattern checking. It
must match the Rx highway data rate which was set in receive highway configu-
ration register (byte 2), HDR[1—0] bits. The transmit highway selection for test-
pattern generation is done using the test-pattern checker highway register. Only
one highway at a time can be involved with test-pattern checking. Test-pattern
generation and checking does not affect the operation of other time slots or high-
ways.
CHKHDR1
0
0
1
1
CHKHDR0
0
1
0
1
Reserved. Read as 0.
2.048 Mbits/s (default)
4.096 Mbits/s
8.192 Mbits/s
0.000 Mbits/s (idle, not receiving data)
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