1417K5A Datasheet, PDF (4/14 Pages) Agere Systems – NetLight 1417K5A 2.5 Gbits/s 1300 nm Laser Transceiver with Clock and Data Recovery

NetLight 1417K5A 2.5 Gbits/s
1300 nm Laser Transceiver with Clock and Data Recovery
Data Sheet
August 2001
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow EIA ^® Stan-
dard EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD.
Agere Systems employs a human-body model (HBM)
for ESD susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent on
the critical parameters used to define the model. A
standard HBM (resistance = 1.5 kΩ, capacitance =
100 pF) is widely used and, therefore, can be used for
comparison purposes. The HBM ESD threshold
established for the 1417K5A transceiver is ±1000 V.
Application Information
The 1417 receiver section is a highly sensitive fiber-
optic receiver. Although the data outputs are digital
logic levels (CML), the device should be thought of as
an analog component. When laying out system appli-
cation boards, the 1417 transceiver should receive the
same type of consideration typically given to a sensitive
analog component.
Printed-Wiring Board Layout Consider-
ations
A fiber-optic receiver employs a very high gain, wide-
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
Noise that couples into the receiver through the power
supply pins can also degrade performance. It is
recommended that a pi filter, shown in Figure 4, be
used for both the transmitter and receiver power
supplies.
Data, Clock, and Signal Detect Outputs
Due to the high switching speeds of CML outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs should be terminated identically. The sig-
nal lines connecting the data outputs to the next device
should be equal in length and have matched imped-
ances. Controlled impedance stripline or microstrip
construction must be used to preserve the quality of
the signal into the next component and to minimize
reflections back into the receiver, which could degrade
its performance. Excessive ringing due to reflections
caused by improperly terminated signal lines makes it
difficult for the component receiving these signals to
decipher the proper logic levels and can cause transi-
tions to occur where none was intended. Also, by mini-
mizing high-frequency ringing, possible EMI problems
can be avoided.
The signal-detect output is positive LVTTL logic. A logic
low at this output indicates that the optical signal into
the receiver has been interrupted or that the light level
has fallen below the minimum signal-detect threshold.
This output should not be used as an error rate indica-
tor, since its switching threshold is determined only by
the magnitude of the incoming optical signal.
VOH
D A T A /C L O C K
VOL
VOH
D A T A /C L O C K
VOL
SINGLE ENDED
D IF F E R E N T IA L
1-1089F.a
Figure 2. Data Input/Output Logic Level Definitions
4
Agere Systems Inc.